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Cedric RECHATIN

GRENOBLE

Electionseuropéennes 2024

RETROUVEZ GRATUITEMENTLe résultat des européennes à Grenoble ainsi que le résultat des européennes dans l'Isère.

En résumé

Analog/Mixed Signal Integrated Circuits Designer
Design of Step-Down DC-DC converters (buck)
PhD. Degree in Microelectronics, CEA/LETI, Grenoble

Technical skills
- Transistors Level Design
- Power Management Circuits (LDO, bandgap...)
- DC-DC converter architecture and design.
- Stability analysis.
- VHDL-AMS Modelization and Mixed Simulation.
- Cadence tools (Spectre, Eldo, AdvanceMS, Virtuoso)
- Laboratory instrumentation for IP validation.


Mes compétences :
Electronique

Entreprises

  • ST MicroElectronics - Ingénieur design analog mixed signal

    2013 - maintenant Analog and mixed Integrated Circuits Designer, Analog, MEMS & Sensors Group
    - Oscillators Design
    - Power Management Circuits (Bandgap, voltage references...)

  • ST Ericsson - Ingénieur design analog mixed signal

    GRENOBLE 2006 - 2013 Analog and mixed Integrated Circuits Designer, IP/Power Management Group, ST- Ericsson, Grenoble

    • Design of Step-Down DC-DC converters (buck) for cellular phone applications in 130nm technology
    • Analog controller design (amplifiers, comparators, ramp generator, current limit…)
    • Design and validation of testchips.
    • IP integration and customization. Top Level simulations
    • Design support for customers. Reliability, testability. Measurement and characterization in Lab.

  • LETI, CEA-Grenoble (France) - PhD thesis in Microelectronics

    PARIS 2003 - 2006 PhD thesis in Microelectronics, Imaging Design Group, CEA/LETI, Grenoble
    “Design on polycrystalline silicon thin film transistors technology (TFT Poly-Si CMOS) for large area electronics applications”
    • Static and dynamic characterizations of TFT Poly-Si
    • TFT Poly-Si modeling: model parameters and matching parameters extraction for circuit simulation
    • Study of architecture for capacitive fingerprint sensors. Elementary pixel implementation with offset voltage cancellation of column charge amplifier.

  • FREESCALE - Engineer internship

    Toulouse 2002 - 2002 Engineer internship, Wireless/Power Management Group, Freescale Semiconductor TOULOUSE
    • Analog design of two low dropout linear regulators (LDO) in BiCMOS 0.35μ technology
    • Layout and electrical tests in laboratory

Formations

Réseau

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